8 group fully discrete R-2R DA modules
to combine into real balanced push/pull decoders.
fully discrete real balanced DSD native decoders.
Fully discrete real balanced current transmition design.
2 pc ultra high frequency 90/98 MHz Accusilicon 318B femtosecond clocks
provide synchronous clock for whole unit without PLL up-frequency .
32bit / PCM384K /DSD512 asynchronous transfer Amanero 384 apply the FPGA
The whole digital circuit built with 1 pc FPGA and 5 pc CPLD programmable
chipsets to separate the different configured circuits for avoid
interrupt, data process in parallel mode.
Support firmware update to improve on
digital process mode settings accessible by buttons on front (No
Firmware update port accessible on rear (Update firmware
need to open the chassis).