R-1  (2021 Version)


 8 group fully discrete R-2R DA modules to combine into real balanced push/pull decoders.

4 group fully discrete real balanced DSD native decoders.

Fully discrete real balanced  current transmition design.

2 pc ultra high frequency 90/98 MHz Accusilicon 318B femtosecond clocks provide synchronous clock for whole unit without PLL up-frequency .

32bit / PCM384K /DSD512 asynchronous transfer Amanero 384 apply the FPGA synchronous clock.

The whole digital circuit built with 1 pc FPGA and 5 pc CPLD programmable chipsets to separate the different configured circuits for avoid interrupt, data process in parallel mode.

Support firmware update to improve on sound quality.

All digital process mode settings accessible by buttons on front  (No need  to open the chassis).
Firmware update port accessible on rear (Update  firmware no need  to open the chassis).