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R-28 2022 Edition

Digital input signal sampling display and simulate vinyl record sound flavor

Fully Balance Discrete Transistors Headamp And Preampamps
All In One

Built in real balanced headphone amp max output power achieve 9500 mW that can drive most headphone easy.

 8 group fully discrete R-2R DA modules to combine into real balanced push/pull decoders.

4 group fully discrete real balanced DSD native decoders.

Fully discrete real balanced  current transmition design.

2 pc ultra high frequency 90/98 MHz Accusilicon 318B femtosecond clocks provide synchronous clock for whole unit without PLL up-frequency .

32bit / PCM384K /DSD512 asynchronous transfer Amanero 384 apply the FPGA synchronous clock.

The whole digital circuit built with 1 pc FPGA and 5 pc CPLD programmable chipsets to separate the different configured circuits for avoid interrupt, data process in parallel mode.

Support firmware update to improve on sound quality.

All digital process mode settings accessible by buttons on front  (No need  to open the chassis).

  

    

       
Please note: The product improve cause the inside or outside change without inform .
Summarize Use Manual Specs Custom Option Shipping Cost

Price:  ( Exclude shipping cost)
R-28 Full upgrade version:  USD1250
The free mini remote controller not in warranty
 
Purchase the metal remote controller simultaneous price is USD38


Please send your address, name  to audio-gd@vip.163.com  get the quote.
Accusilicon clocks:

       

Click to download the driver of  Amanero combo 384

Unique Jitter elimination technology:
        Jitter has always been regarded as the root cause for sound quality of digital systems to be inferior to that of high-end analog systems.
       In some traditional DAC designs, the clock processing method is to follow and to restore the clock of the signal source, and some designs also include the capacity of reducing jitter, but with limitations when the jitter level is large.
      This common solution allows getting good measurements in lab tests. But in actual use, most signal sources have large jitter levels, so that the resulting sound quality will not be satisfactory.
       Some DACs worth only USD150 measure better then than some well-selling DACs of foreign brands worth tens of thousands. Who would think that this USD150 DAC is better? This reminds me of when the China Insurance Research Institute tested a direct collision between two brands of cars not long ago, and netizens commented on the car that scored higher in the test: "It has not failed the test, but it has not won the actual battle either."
       The following three product charts are from three DACs of different brands, guess which one is the most expensive? (The answer is at the bottom of this page)

Product A
       
Product B
         Product C
         
          In order to completely eliminate the influence of jitter in the incoming signal, the R8 MK2 uses an asynchronous clocking process.
          First it reads and stores a considerable amount of signal source data to RAM, discard the clock of the signal source, and directly use the high-performance built-in Accusilicons to clock the output from the RAM. Since both data and clock are handled by the FPGA, the impact of transmission on jitter is neglectable. The jitter level is essentially the same as what is specified for the TCXO clocks used by the R8 MK2.

               
       

         The key to this processing method is to ensure the integrity of data transmission, which is our technical secret. Realize that as soon as a single data sample within a million is lost in the transmission, a sharp and obvious cracking sound, like static, or a scratch on a vinyl, will be heard during playback.

        Mr. He is passionate about music and, too him, listening sessions are a source of inspiration for new design ideas. Our cie does not only have the advantage of having full control over software and hardware technology, we also possess a correct understanding of music reproduction.  Without having to rely on outsourcing for R&D, we can at any moment listen to the gears during development, allowing the pursuit and realization of the most realistic sound reproduction.

        Because the local clock and the signal source clock are completely isolated and run independently, the traditional jitter measurement methods can not be applied, instead a special data acquisition circuit is required to evaluate its level. For human beings, the best test method is always through listening tests. A jitter-free sound is very realistic and natural, as clear as pure water, and very involving.



R-28 2022 Edition feature:

1,     Digital input signal sampling display and simulate vinyl record sound flavor .(New Feature)
2,     USB  transmit the IIS signal to the FPGA processor and receive the clock signal from the FPGA processor, the USB interface without on board data clocks, the signal transmit is much exact, the sound quality get the much improve , close to the last generative R-28 combine with DI-20 (But not DI-20HE) level. (New Feature)
3,      The FPGA process data in the  parallel mode.
         The IIS data is series transmit mode, every data must need one clock cycle to process or transmit, one frame data ( Include L and R data) must need 64 clock cycle to process or transmit, so the data has effect by the 64 clock cycles.
         But the parallel data process and transmit mode only need one clock cycle can finish the one frame data process and transmit, that can avoid the effect of clock stability .
          The IIS input (Include USB and HDMI-IIS) has recombine become dual 32bit parallel data once input , and the SPDIF input after decoder, has recombine become dual 24bit parallel data, and the DSD input has recombine become dual 64bit parallel data once input.
          The parallel process and transmit mode can improve the sound quality on the transparency and detail but still analog.
4,       Full new configuration clock manage design built in, improved on the clock timing.
5,      DSD asynchronous clock technology has apply that improves the sound quality obviously.
6,      DOP support from SPDIF input .

7,       Dual transformers power supply separately.
8,      
The unit has two gain modes, the 12DB on low gain for drive the headphone which has over 95DB sensitivity, and 22DB on high gain cooperate with the strong power ability,  enough to drive the HE6 which has around 85DB sensitivity headphones.If customer want to boost 6-12DB gain, in total 28-34DB gain.

Pros and cons of R-2R DAC  :
Advantages:
         1.R-2R will not convert the clock signal into the output signal.
         2. R-2R is not sensitive to jitter .Delta-Sigma D/A is much more sensitive to jitter.
         3. The output signal is much more precise compared to Delta-Sigma D/A .
Weaknesses:
        1.THD today is extremely good with Sigma Delta chips in comparison to R2R ladders are good too but not as good.
        2. Glitches and accuracy of the ladder resistors are very difficult to avoid and require complex technology to resolve it.


R-2R basic design in the market:
 
        
 The R-2R DAC is very popular nowadays and available from DIY kits up to  completely   high-end products. 
          In the low range DIY market, the R-2R design is often based on old technology designed a long time ago by MSB and only includes basic R2R ladder design and do not include the wonderful correction design of the original MSB technology. This design uses data shift registers logic chips in series mode to convert the data to an analog signal. The structural R2R technology issues cannot be avoided, and performance is solely depending on the accuracy of the ladder resistors. 
        


         
In the High-End market the R2R design is much more complex and achieves better performance. A basic R2R ladder is simply not sufficient enough to achieve good performance and high sound quality! Some manufacturers are using shift registers design. A less complex and less efficient design based on traditional logic chips working in serial mode to correct the ladder.
         A far better design switches resistors in parallel mode. An ultra-fast FPGA controls and corrects the R2R ladder. The parallel design mode controls every bit respectively and therefore achieve unprecedented performance. (In parallel mode only 1 clock cycle is needed to output all data; serial design mode needs at minimum 8 up to 24 clock cycles) The parallel design is much more complicated. Once designed properly it can correct every bit of the ladder.  Photo below shows a design with such FPGA,  can correct the unavoidable imperfections of the R2R ladder caused by intolerance of resistors glitches and achieve  best performance.

         


Accuracy of the ladder resistors (tolerance):
               
  Many people believe the tolerance of the resistors in the ladder is most important to reach best performance. Nowadays 24 bit resolution is standard. What tolerance is needed to achieve 24 bit resolution?
            When we look at 16 bit the tolerance of 1/66536, 0.1% (1/1000) is far not enough, even a tolerance of 0.01% (1/10000), the best tolerance available in the world today, still cannot handle 16 bit correctly; we are not even calculating 24 bit here!
           The tolerance of the resistor will never solve Imperfections of a ladder. This would require resistors with a tolerance of 0.00001% and ability to  handle 24 bit resolution. This is only in theory because the discreteness of the switch logic chips have already too much internal impedance and will destroy the impossible tolerance of a the resistor.
            The solution is to correct the ladder and not to depend on the tolerance of resistors. Its a combination of both: Ultra-low tolerance resistors controlled by a correction technology and very high speed FPGA which is applied  in in our design.

           

Importunacy of the FPGA/CPLD:
               
 FPGA stands for Programmable Array Logic. 
            Nowadays the FPGA is applied in a lot high end grade DACs; like the popular ROCKNA WAVEDREAM DAC. 
            We have applied the FPGA in our DAC products since 2008.
            R-7 has built in 1 pc FPGA and 5 pc CPLD programmable chipsets to separate the different configured circuits for avoid interrupt.
            The internal hardware design is fully controlled by complex software. A huge advantage is the fact the software in the FPGA can easily be upgraded offering new features or improve the performance. Such design is much flexible and future proof!

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FPGA/CPLD tasks :
           1. The FPGA high performance SPDIF interface, replacing traditional  SPDIF interface chips like DIR9001, WM8805 or AK411X wich are lower in performance in comparison to FPGA.

           2. Full re-clocking process with FIFO design applicable on all inputs. This way the output data keeps fully synchronized with the clock signal to reject any jitter.
           3. Built in 2X, 4X and 8X oversampling and digital filters and on top of this 4 different true NOS (only analog 6dB filtering) modes. To completely configure it to your liking!
           4. Built in the especial design to simulate the vinyl record sound flavor.
          

Built in an excellent real balance discrete amp
              
 The signal last stage is the analog output stages, which have paramount  effect the final DAC sound quality. 
          After d/a conversion by the R2R D/A modules the analogue signal is transported by fully discrete matched-transistor output stages. 
          The high speed special ACSS output stages are non-feedback and current driven design. 
          They are Special because almost all other designs need to convert the signal multiple times from and to current or voltage, resulting in less detail and less defined soundstage .
          
The output stages have built in  4 pair 15W transistors  to offer strong drive capanility .The diamond differential  design can avoid switch distortion , it is working in a class A but don't draw large  current while idle . The balance drive mode can kill the noise and distortion and improves the soundstage presentation ,background and the transparency ,ect.
         
     


0.05% tolerance volume control system
             
  There 4 channels volume boards are  built in into the unit for a balance volume are control by digital signal applied relaies control the resistors in analog area . The 0.1% Vishay or KOA resistors working in parallel mode to got the 0.05% tolerance . ( I dont know technical design so I cant correct this part)


Heavy power supplies design:
                
 The DAC has the high quality low noise, low flux leakage, R-cores transformers to supply all digital parts as well as left and right analog boards. 
            There are in total 11 groups ultra-high speed and ultra-low noise PSUs built in and applied in a double stage PSUs technology for stable power delivery. That design allowes get very clean power supply for the digital parts of DAC.
             There are two groups of pure class A PSUs built in for the analog amps .

           
  

Answer
Product A GUSD150 DAC

Product B GUSD5000+ DAC American P brand DAC
 
Product C G USD10000  British E brand RIAA front
 

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